Contractor
פרויקט מס' 192300
Job Statistics
3 Bids |
תקציב
25,000 ₪ - 50,000 ₪
|
תוקף הפרויקט
סגור להצעות נוספות
|
טווח הצעות
150
₪
-
440
₪
לשעת עבודה
|
הצעה ממוצעת
246
₪
לשעת עבודה
|
Job Info And Actions
תאריך פרסום:
14:43, 9 אוקטובר, 2023
הצעות תתקבלנה עד:
22:30, 21 אוקטובר, 2023
Contractor
Looking for contractor to do the following project:
1. Implement a device reader i/f of angles and velocity and time stamp.
2. Take all values and extends the packet header by 16 bytes
3. Add a read and write to Zynq in 7ev of the value of angles and velocity
4. As a result you need to read and write without harming the reading of the header that comes after image read.
Support read action, write action, read burst before and after header operation, keep a safe gap to finish any read before
5. Implement ID register reading
6. Implement a burst read to be sure the right values for angles and velocity and time stamp are refered to same time.
7. Update HSID file with register field and functional description
8. Write RTL, Write Test bench
9. Merge the simulation to image testbench and simulation
10. Read Data Sheet of device with up to 100 registers, filters and other
11. Write C programs in Vitis, when checking the values that read from Zynq, and changing the board angle and velocity to check that reasonable number are being received
12. For some reason there is a bug in board and reset is not connected , so you need to implement a software reset,
13. As the device has flash inside, you must
14. For Debug of header extension, enable Zynq read for those registers
15. Look carefully in the timing, the timing and order of writing and reading is different
16. Do it configurable of frequency, commands that are sent and modulrity.
17. In another project integrate Uart - interrupts, connect proper registers
18. Integrate with SW Engineer
19. Explore a voltage monitor design and do reverse engineering to see the failing points in design.
1. Implement a device reader i/f of angles and velocity and time stamp.
2. Take all values and extends the packet header by 16 bytes
3. Add a read and write to Zynq in 7ev of the value of angles and velocity
4. As a result you need to read and write without harming the reading of the header that comes after image read.
Support read action, write action, read burst before and after header operation, keep a safe gap to finish any read before
5. Implement ID register reading
6. Implement a burst read to be sure the right values for angles and velocity and time stamp are refered to same time.
7. Update HSID file with register field and functional description
8. Write RTL, Write Test bench
9. Merge the simulation to image testbench and simulation
10. Read Data Sheet of device with up to 100 registers, filters and other
11. Write C programs in Vitis, when checking the values that read from Zynq, and changing the board angle and velocity to check that reasonable number are being received
12. For some reason there is a bug in board and reset is not connected , so you need to implement a software reset,
13. As the device has flash inside, you must
14. For Debug of header extension, enable Zynq read for those registers
15. Look carefully in the timing, the timing and order of writing and reading is different
16. Do it configurable of frequency, commands that are sent and modulrity.
17. In another project integrate Uart - interrupts, connect proper registers
18. Integrate with SW Engineer
19. Explore a voltage monitor design and do reverse engineering to see the failing points in design.
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